Xpll Clkout Control (Xpllclkcfg) Register; Usb Pll Configuration (Upllctl) Register; Master Subsystem Clock Divider (M3Ssdivsel) Register Field Descriptions; Xpll Clkout Control (Xpllclkcfg) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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System Control Registers

Table 1-107. Master Subsystem Clock Divider (M3SSDIVSEL) Register Field Descriptions

1.13.7.5 XPLL CLKOUT Control (XPLLCLKCFG) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-108. XPLL CLKOUT Control (XPLLCLKCFG) Register Field Descriptions

XPLLCLKOUTDI

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

System Control and Interrupts

M3 Subsystem Clock Divide

This bit selects between /4, /2, and /1 for the M3 sub-system clock. The C28 CLKIN clock is divided

by the below ratios to generate the M3 SS clock. The configuration of the M3SSDIVSEL bits is as

Select M3SS clock divide By 1 of PLLYSCLK clock

Select M3SS clock divide By 2 of PLLYSCLK clock

Select M3SS clock divide By 4 of PLLSYSCLK clock

Figure 1-97. XPLL CLKOUT Control (XPLLCLKCFG) Register

XPLLCLKOUT Divide Ratio

This bit selects a clock divide ratio for the XPLLCLKOUT clock. The configuration of the

XPLLCLKOUTDIV bits is as follows.

For Rev0 Devices only

XPLLCLKOUT is off

Select XPLLCLKOUT = PLLSYSCLKC28

Select XPLLCLKOUT = PLLSYSCLK /2

Select XPLLCLKOUT = PLLSYSCLK /4 (default)

For RevA Devices and newer

XPLLCLKOUT is off

Select XPLLCLKOUT = C28 SYSCLK/4

Select XPLLCLKOUT = M3 SSCLK/4

Select XPLLCLKOUT = PLLSYSCLK/4 (default)

Figure 1-98. USB PLL Configuration (UPLLCTL) Register

SPRUH22I – April 2012 – Revised November 2019

XPLLCLKOUTDIV

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