Dma Channel Control Word (Dmachctl), Offset 0X008; Dma Channel Control Word (Dmachctl) Register; Dma Channel Destination Address End Pointer (Dmadstendp) Register Field Descriptions; Dma Channel Control Word (Dmachctl) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

µDMA Channel Control Structure
Table 16-15. DMA Channel Destination Address End Pointer (DMADSTENDP) Register Field
Bit Field
31-0 ADDR

16.6.3 DMA Channel Control Word (DMACHCTL), offset 0x008

DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used to specify
parameters of a µDMA transfer.
NOTE: The offset specified is from the base address of the control structure in system memory, not
the µDMA module base address.
31 30
DSTINC
R/W
23
15 14
ARBSIZE
R/W
7
XFERSIZE
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-16. DMA Channel Control Word (DMACHCTL) Register Field Descriptions
Bit Field
31-30 DSTINC
1172
M3 Micro Direct Memory Access ( µDMA)
Value Description
Destination Address End Pointer
This field points to the last address of the µDMA transfer destination (inclusive). If the destination
address is not incrementing (the DSTINC field in the DMACHCTL register is 0x3), then this field
points at the destination location itself (such as a peripheral data register).
Figure 16-9. DMA Channel Control Word (DMACHCTL) Register
29 28
DSTSIZE
R/W
Reserved
R/W
13
4
R/W
Value Description
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value of the destination size
(DSTSIZE).
0x0 Byte
Increment by 8-bit locations
0x1 Half-word
Increment by 16-bit locations
0x2 Word
Increment by 32-bit locations
0x3 No increment
Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the
channel
Copyright © 2012–2019, Texas Instruments Incorporated
Descriptions
27 26
SRCINC
R/W
18
XFERSIZE
R/W
3 2
NXTUSEBURS
T
R/W
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25 24
SRCSIZE
R/W
17 16
ARBSIZE
R/W
8
0
XFERMODE
R/W
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