Flash Registers Memory Map On Master Subsystem - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Flash Registers
5.4 Flash Registers
The M3 flash/OTP memory and C28x flash can be configured by the registers shown in
Table 5-85, respectively. All the control subsystem flash registers are protected by the code security
module. For master subsystem flash registers, the SECZONEREQUEST semaphore register (mapped at
address 0x400FA160) is provided for accessing the flash registers for the two M3 security zones, with out
compromising on security.
The flash control registers should not be written to by code that is running from OTP or flash memory or
while an access to flash or OTP is in progress. All register accesses to the flash registers should be made
from code executing outside of flash/OTP memory; an access should not be attempted until all activity on
the flash/OTP has completed. No hardware is included to protect against this. To summarize, you can
read the flash registers from code executing in flash/OTP; however, do not write to the registers.
CPU write access to the flash registers can be enabled only by executing the EALLOW instruction on the
C28x core and by initializing MWRALLOW with 0xA5A5A5A5 on Cortex-M3. Write access to flash
registers is disabled when the EDIS instruction is executed on the C28x core. For Cortex-M3, write access
to flash registers is disabled when MWRALLOW is initialized with any value other than 0xA5A5A5A5. This
protects the registers from spurious accesses. The registers can be accessed through the JTAG port
without the need to execute EALLOW/initialize MWRALLOW.
Register Register
Acronym Description
Flash Control Registers
FRDCNTL Flash Read
Control Register
FSPRD Flash read
margin control
register
Reserved Reserved
FBAC Flash Bank
Access Control
Register
FBFALLBACK Flash Bank
Fallback Power
Register
FBPRDY Flash Bank
Pump Ready
Register
FPAC1 Flash Pump
Access Control
Register 1
FPAC2 Flash Pump
Access Control
Register 2
FMAC Flash Module
Access Control
Register
FMSTAT Flash Module
Status Register
(Used with Flash
API – Refer to
Flash Application
Programming
Interface User's
Specification for
details of this
register)
Reserved Reserved
508
Internal Memory
Table 5-84. Flash Registers Memory Map on Master Subsystem
Size (x8)
4
4
52
4
4
4
4
4
4
4
264
Copyright © 2012–2019, Texas Instruments Incorporated
Type M3 Offset (0x8) M3 Protection
R/W 0x0
R/W 0x4
R/W 0x03C
R/W 0x040
R 0x044
R/W 0x048
R/W 0x04C
R 0x050
R 0x054
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 5-84 and
Reset Source
0x400F:A000
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
MWRALLOW M3SYSRSTn
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