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All uncorrectable double-bit errors end up triggering a BUS FAULT on the master subsystem's CPU and
an NMI on the control subsystem. A RAMACCVIOL on the master subsystem triggers a BUSFAULT
exception on and triggers a PIE interrupt on the control subsystem.
1.6.8 ECC Enabled Flash Memory
Flash single-bit errors are corrected automatically by ECC logic before giving data to the CPU, but they
are not corrected in flash memory. Flash memory will still contain wrong data until another erase/program
operation happens to correct the flash contents. Irrespective of whether the error interrupt is enabled or
disabled, single bit errors are always corrected before giving data to the CPU. When the interrupt is
disabled, users can check the single-bit error counter register (M3_ ERR_CNT) for any single bit error
occurrences. The error counter stops incrementing once its value is equal to the threshold+1. It is always
suggested to set the threshold register to a non-zero value so that the error counter can increment. It is up
to the user to decide the threshold value at which they have to reprogram the flash with the correct data.
Flash uncorrectable errors end up triggering a BUSFAULT to the master subsystem's CPU and an NMI to
the control subsystem. Please refer to the Internal Memory chapter of this document for more details on
flash error correction and error catching mechanisms.
1.7
Power Control
The on-chip 1.2v and 1.8v VREGs generate the 1.2v VDD signal and 1.8v VDD signal from the 3.3
input as needed to power the digital and analog subsystems on the device. This is done by pulling the -
VREG12EN and -VREG18EN pins low. Refer to the device data manual for more details on these pins.
Users can also choose to provide an external 1.2v VDD signal and 1.8v VDD signal instead of using the
on-chip VREGs. In this case, both the VREG12EN and VREG18EN pins should be pulled high.
The 3.3v input supply is monitored by the power-on rest (POR) circuit during a power-on condition. If a
POR is detected, the XRS and ARS pins are pulled low to keep the device in reset.
The 1.8v VDD supply, when generated by the on-chip 1.8v VREG, is monitored by the power-on reset
(POR) during a power-on condition. If a POR is detected, the XRS and ARS pins are pulled low to keep
the device in reset.
The 1.2v VDD supply, when generated by the on-chip 1.2v VREG, is monitored by the power-on reset
(POR) during a power-on condition. If a POR is detected, the XRS and ARS pins are pulled low to keep
the device in reset.
1.8
Clock Control
The clocking control module has multiple sections covering the master subsystem clocking, control
subsystem clocking, analog subsystem clocking, device low power modes clocking, and device attributes
and configurations. There are configuration and status registers for each subsystems' clocking, device
configurations, and low power mode configurations.
The master subsystem is responsible for clocking control and can read/write to clocking configuration
registers by default on reset. The PLL and SYSDIVSEL registers are read only by default by the control
subsystem, and the control subsystem can gain write-access to these registers by claiming the clock
control semaphore register, CCLKREQUEST.
The master subsystem can also choose to switch off the clock for the control subsystem by setting the
C28CLKINDIS (bit 0) of the CCLKOFF register. The clock to the control subsystem is enabled by default
on power-up and after an XRS.
Shared RAM, IPCs, and message RAMs, which are shared resources between the master and control
subsystems, are clocked by the shared resource clock, which is the same as the PLLSYSCLK. Refer to
the Internal Memory chapter for more details on shared resources.
Refer to the clocking diagrams in the master and control subsystems for more details on these clock
sources.
SPRUH22I – April 2012 – Revised November 2019
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Safety Features
VDDIO
System Control and Interrupts
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