Introduction; I2C Block Diagram; Functional Description - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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22.1 Introduction

The M3 Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a

serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial

memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may

also be used for system testing and diagnostic purposes in product development and manufacture. The

microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with

other I2C devices on the bus.

The two I2C modules include the following features:

Devices on the I2C bus can be designated as either a master or a slave

– Supports both transmitting and receiving data as either a master or a slave

– Supports simultaneous master and slave operation

Four I2C modes

– Master transmit

– Master receive

– Slave transmit

– Slave receive

Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)

Master and slave interrupt generation

– Master generates interrupts when a transmit or receive operation completes (or aborts due to an

– Slave generates interrupts when data has been transferred or requested by a master or when a

START or STOP condition is detected

Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

shows the block diagram for I2C.

Each I2C module is comprised of both master and slave functions. For proper operation, the SDA and

SCL pins must be configured as open-drain signals. A typical I2C bus configuration is shown in

See Inter-Integrated Circuit (I2C) Interface electricals in the device data manual for I2C timing diagrams.

SPRUH22I – April 2012 – Revised November 2019

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Figure 22-1. I2C Block Diagram

C MasterCore

M3 Inter-Integrated Circuit (I2C) Interface

Introduction

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