Gpio Interrupt Both Edges (Gpioibe) Register; Gpio Interrupt Event (Gpioiev) Register; Gpio Interrupt Both Edges (Gpioibe) Register Field Descriptions; Gpio Interrupt Event (Gpioiev) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.6.4 GPIO Interrupt Both Edges (GPIOIBE) Register, offset 0x408
The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register is set to detect edges, setting a bit in the GPIOIBE register configures
the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the
GPIO Interrupt Event (GPIOIEV) register. Clearing a bit configures the pin to be controlled by the
GPIOIEV register. All bits are cleared by a reset.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-9. GPIO Interrupt Both Edges (GPIOIBE) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 IBE
4.1.6.5 GPIO Interrupt Event (GPIOIEV) Register, offset 0x40C
The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the
GPIO Interrupt Sense (GPIOIS) register. Clearing a bit configures the pin to detect falling edges or low
levels, depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-10. GPIO Interrupt Event (GPIOIEV) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 IEV
350
General-Purpose Input/Output (GPIO)
Figure 4-7. GPIO Interrupt Both Edges (GPIOIBE) Register
R-0
Value Description
Reserved
GPIO Interrupt Both Edges
0 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register.
1 Both edges on the corresponding pin trigger an interrupt.
Figure 4-8. GPIO Interrupt Event (GPIOIEV) Register
R-0
Value Description
Reserved
GPIO Interrupt Event
0 A falling edge or a Low level on the corresponding pin triggers an interrupt.
1 A rising edge or a High level on the corresponding pin triggers an interrupt.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
Reserved
R-0
8 7
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
IBE
R/W-0
IEV
R/W-0
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