Counter-Compare A And Mirror 2 Register (Cmpa / Cmpam2); Compare A High-Resolution Mirror Register (Cmpahrm); Counter-Compare A Mirror Register (Cmpam); Counter-Compare A And Mirror 2 Register (Cmpa / Cmpam2) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 7-90. Counter-Compare A and Mirror 2 Register (CMPA / CMPAM2)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-40. Counter-Compare A and Mirror 2 Register (CMPA / CMPAM2) Field Descriptions
Bit Field Description
15-0 CMPA The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the
values are equal, the counter-compare module generates a "time-base counter equal to counter compare A"
event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions.
These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration
of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB
registers include:
• Do nothing; the event is ignored.
• Clear: Pull the EPWMxA and/or EPWMxB signal low
• Set: Pull the EPWMxA and/or EPWMxB signal high
• Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this
register is shadowed.
• If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically go to
• Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is currently
• If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go directly
• In either mode, the active and shadow registers share the same memory map address.
Figure 7-91. Compare A High-Resolution Mirror Register (CMPAHRM)
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-41. Compare A High-Resolution Mirror Register (CMPAHRM) Field Descriptions
Bit Field
15-8 CMPAHR
7-0 Reserved
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event will load the
active register from the shadow register.
full.
to the active register, that is the register actively controlling the hardware.
Value Description
00-FFh Compare A High-Resolution Bits
Writes to both the CMPAHR and CMPAHRM locations access the high-resolution (least significant
8-bit) portion of the Counter Compare A value. The only difference is that unlike CMPAHR, reads
from the mirror register, CMPAHRM, are indeterminate (reserved for TI Test).
By default writes to this register are shadowed. Shadowing is enabled and disabled by the
CMPCTL[SHDWAMODE] bit as described for the CMPAM register.
Reserved for TI test.
Figure 7-92. Counter-Compare A Mirror Register (CMPAM)
Copyright © 2012–2019, Texas Instruments Incorporated
CMPA
R/W-0
CMPAHR
R/W-0
Reserved
R-0
CMPA
R/W-0
C28 Enhanced Pulse Width Modulator (ePWM) Module
Registers
0
8
0
0
745