Lx Ram Test And Initialization Register 1 (Clxrtestinit1); Lx Ram Test And Initialization Register 1 (Clxrtestinit1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.2.3.8

Lx RAM Test and Initialization Register 1 (CLxRTESTINIT1)

Figure 5-48. Lx RAM Test and Initialization Register 1 (CLxRTESTINIT1)
31
7 6
ECCPARTEST RAMINITL3
L3
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-53. Lx RAM Test and Initialization Register 1 (CLxRTESTINIT1) Field Descriptions
Bit Field
31-8 Reserved
7 ECCPARTESTL3
6 RAMINITL3
5 ECCPARTESTL2
4 RAMINITL2
3 ECCPARTESTL1
2 RAMINITL1
1 ECCPARTESTL0
0 RAMINITL0
SPRUH22I – April 2012 – Revised November 2019
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5 4
ECCPARTEST RAMINITL2
L2
R/W-0 R/W-0
Value Description
Reserved
Enable/Disable RAMTEST Feature for L3 RAM Block
0 RAMTEST feature is disabled for L3 RAM block.
1 RAMTEST feature is enabled for L3 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization L3. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of L3 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
Enable/Disable RAMTEST Feature for L2 RAM Block
0 RAMTEST feature is disabled for L2 RAM block.
1 RAMTEST feature is enabled for L2 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization L2. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of L2 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
Enable/Disable RAMTEST Feature for L1 RAM Block
0 RAMTEST feature is disabled for L1 RAM block.
1 RAMTEST feature is enabled for L1 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization L1. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of L1 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
Enable/Disable RAMTEST Feature for L0 RAM Block
0 RAMTEST feature is disabled for L0 RAM block.
1 RAMTEST feature is enabled for L0 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization L0. Any reads to this bit will return a 0.
0 No action taken.
1 Initialize all address locations of L0 RAM block with data 0x0 and corresponding data an address
ECC/parity bits.
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Reserved
R-0
3 2
ECCPARTEST RAMINITL1
L1
R/W-0 R/W-0
RAM Control Module Registers
8
1 0
ECCPARTEST RAMINITL0
L0
R/W-0 R/W-0
Internal Memory
473