Parity Error Code Register (Can Perr); Auto-Bus-On Time Register (Can Abotr); Parity Error Code Register (Can Perr) [Offset = 0X1C]; Parity Error Code Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

Advertisement

www.ti.com
Bit
Field
2-0
Reserved
For all test modes, the Test bit in CAN Control register needs to be set to one. If Test bit is set, the EXL,
Tx1, Tx0, LBack and Silent bits are writable. Bit Rx monitors the state of pin CAN_RX and therefore is
only readable. All Test register functions are disabled when the Test bit is cleared.
NOTE: The Test register is only writable if Test bit in CAN Control register is set.
NOTE: Setting Tx[1:0] other than '00' will disturb message transfer.
NOTE: When the internal loopback mode is active (bit LBack is set), bit EXL will be ignored.

23.15.7 Parity Error Code Register (CAN PERR)

The Parity Error Code register (CAN PERR) is shown and described in the figure and table below.
Figure 23-25. Parity Error Code Register (CAN PERR) [offset = 0x1C]
31
15
Reserved
R-0
LEGEND: R = Read; -n = value after reset; -U = Undefined
Bit
Field
31-11
Reserved
10-8
Word Number
7-0
Message Number
If a parity error is detected, the PER flag will be set in the Error and Status Register. This bit is not reset
by the parity check mechanism; it must be reset by reading the Error and Status Register. In addition to
the PER flag, the Parity Error Code Register will indicate the memory area where the parity error has been
detected (message number and word number).
If more than one word with a parity error was detected, the highest word number with a parity error will be
displayed.
After a parity error has been detected, the register will hold the last error code until power is removed.

23.15.8 Auto-Bus-On Time Register (CAN ABOTR)

The Auto-Bus-On Time register (CAN ABOTR) is shown and described in the figure and table below.
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Table 23-10. Test Register Field Descriptions (continued)
Value
Description
Reserved
11
10
Word Number
R-U
Table 23-11. Parity Error Code Register Field Descriptions
Value
Description
Reserved
0x01-0x05
Word number where parity error has been detected RDA word number (1 to 5) of the
message object (according to the Message RAM representation in RDA mode, see
Section
23.14.3).
0x01-0x80
Message object number where parity error has been detected
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8
7
CAN Control Registers
Message Number
R-U
M3 Controller Area Network (CAN)
16
0
1551

Advertisement

Table of Contents
loading

Table of Contents