Table of Contents
Advertisement
C-Boot ROM Description
6.6.14.7 C-Boot ROM Parallel Boot Mode Protocol
The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from GPIO0 -GPIO5,
GPIO8-GPIO9 to internal memory. Each value is 8 bits long and follows the same data flow as outlined in
Figure
6-28.
Figure 6-28. Overview of Parallel GPIO Bootloader Operation
Control
subsystem
boot ROM
The control subsystem communicates with the external host device by polling/driving the GPIO27 and
GPIO26 lines. The handshake protocol shown in
word via GPIO [9,8,5:0]. This protocol is very robust and allows for a slower or faster host to communicate
with the master subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The most significant byte (MSB) is read
first followed by the least significant byte (LSB). In this case, data is read from GPIO[9,8,5:0].
The 8-bit data stream is shown in
610
ROM Code and Peripheral Booting
28x control − GPIO26
Host control − GPIO27
8
Data GP I/O port GPIO[9,8,5:0]
Figure 6-29
Table
6-30.
Copyright © 2012–2019, Texas Instruments Incorporated
Host
(data and program
source)
must be used to successfully transfer each
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com
Advertisement
Chapters
Table of Contents
