Cpu Interrupt Enable Register (Ier); Cpu Interrupt Enable Register (Ier) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers
When a hardware interrupt is serviced or an INTR instruction is executed, the corresponding IER bit is
cleared automatically. When an interrupt is requested by the TRAP instruction the IER bit is not cleared
automatically. In the case of the TRAP instruction if the bit needs to be cleared it must be done by the
interrupt service routine.
At reset, all the IER bits are cleared to 0, disabling all maskable CPU level interrupts.
The IER register is shown in
15 14
RTOSINT DLOGINT
R/W-0 R/W-0
7 6
INT8 INT7
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-86. CPU Interrupt Enable Register (IER) Field Descriptions
Bits Field
15 RTOSINT
14 DLOGINT
13 INT14
12 INT13
11 INT12
10 INT11
9 INT10
8 INT9
7 INT8
6 INT7
212
System Control and Interrupts
Figure 1-75, and descriptions of the bits follow the figure.
Figure 1-75. CPU Interrupt Enable Register (IER)
13 12
INT14 INT13
R/W-0 R/W-0
5 4
INT6 INT5
R/W-0 R/W-0
Value Description
Real-time operating system interrupt enable. RTOSINT enables or disables the CPU RTOS
interrupt.
0 Level INT6 is disabled
1 Level INT6 is enabled
Data logging interrupt enable. DLOGINT enables or disables the CPU data logging interrupt.
0 Level INT6 is disabled
1 Level INT6 is enabled
Interrupt 14 enable. INT14 enables or disables CPU interrupt level INT14.
0 Level INT14 is disabled
1 Level INT14 is enabled
Interrupt 13 enable. INT13 enables or disables CPU interrupt level INT13.
0 Level INT13 is disabled
1 Level INT13 is enabled
Interrupt 12 enable. INT12 enables or disables CPU interrupt level INT12.
0 Level INT12 is disabled
1 Level INT12 is enabled
Interrupt 11 enable. INT11 enables or disables CPU interrupt level INT11.
0 Level INT11 is disabled
1 Level INT11 is enabled
Interrupt 10 enable. INT10 enables or disables CPU interrupt level INT10.
0 Level INT10 is disabled
1 Level INT10 is enabled
Interrupt 9 enable. INT9 enables or disables CPU interrupt level INT9.
0 Level INT9 is disabled
1 Level INT9 is enabled
Interrupt 8 enable. INT8 enables or disables CPU interrupt level INT8.
0 Level INT8 is disabled
1 Level INT8 is enabled
Interrupt 7 enable. INT7 enables or disables CPU interrupt level INT7.
0 Level INT7 is disabled
1 Level INT7 is enabled
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
INT12 INT11
R/W-0 R/W-0
3 2
INT4 INT3
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
9 8
INT10 INT9
R/W-0 R/W-0
1 0
INT2 INT1
R/W-0 R/W-0
Submit Documentation Feedback