Dma Alternate Channel Control Base Pointer (Dmaaltbase), Offset 0X00C; Dma Channel Wait-On-Request Status (Dmawaitstat), Offset 0X010; Dma Channel Software Request (Dmaswreq), Offset 0X014; Dma Alternate Channel Control Base Pointer (Dmaaltbase) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 16-19. DMA Channel Control Base Pointer (DMACTLBASE) Register Field Descriptions
Bit Field
31-10 ADDR
9-0 Reserved

16.7.4 DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C

The DMAALTBASE register returns the base address of the alternate channel control data. This register
removes the necessity for application software to calculate the base address of the alternate channel
control structures. This register cannot be read when the µDMA controller is in the reset state.
Figure 16-13. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-20. DMA Alternate Channel Control Base Pointer (DMAALTBASE) Register Field
Bit Field
31-0 ADDR

16.7.5 DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010

This read-only register indicates that the µDMA channel is waiting on a request. A peripheral can hold off
the µDMA from performing a single request until the peripheral is ready for a burst request to enhance the
µDMA performance. The use of this feature is dependent on the design of the peripheral and is not
controllable by software in any way. This register cannot be read when the µDMA controller is in the reset
state.
Figure 16-14. DMA Channel Wait-on-Request Status (DMAWAITSTAT) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-21. DMA Channel Wait-on-Request Status (DMAWAITSTAT) Register Field Descriptions
Bit Field
31-0 WAITREQ[n]

16.7.6 DMA Channel Software Request (DMASWREQ), offset 0x014

Each bit of the DMASWREQ register represents the corresponding µDMA channel. Setting a bit generates
a request for the specified µDMA channel.
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Channel Control Base Address
This field contains the pointer to the base address of the channel control table. The base address
must be 1024-byte aligned.
Reserved
Value Description
Alternate Channel Address Pointer
This field provides the base address of the alternate channel control structures.
Value Description
Channel [n] Wait Status
These bits provide the channel wait-on-request status. Bit 0 corresponds to channel 0.
0 The corresponding channel is not waiting on a request.
1 The corresponding channel is waiting on a request.
Copyright © 2012–2019, Texas Instruments Incorporated
ADDR
R-0000.0200
Descriptions
WAITREQ[n]
R-0
M3 Micro Direct Memory Access ( µDMA)
µDMA Register Descriptions
0
0
1177