Nested Vectored Interrupt Controller (Nvic) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
wrap value.
• SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the
value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing
the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the
COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not
trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the
register is accessed.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the
SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers.
Note: When the processor is halted for debugging, the counter does not decrement.

25.2.2 Nested Vectored Interrupt Controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The
NVIC supports:
• 53 interrupts
• A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority,
so level 0 is the highest interrupt priority
• Low-latency exception and interrupt handling
• Level and pulse detection of interrupt signals
• Dynamic reprioritization of interrupts
• Grouping of priority values into group priority and subpriority fields
• Interrupt tail-chaining
• An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit,
with no instruction overhead, providing low latency exception handling.
25.2.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as
edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this
happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse
interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure
the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle,
during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see
Hardware and Software Control of Interrupts below for more information). For a level-sensitive interrupt, if
the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt
signal asserted until it no longer needs servicing.
25.2.2.2 Hardware and Software Control of Interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
• The NVIC detects that the interrupt signal is High and the interrupt is not active.
• The NVIC detects a rising edge on the interrupt signal.
• Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the
PEND0 register or SWTRIG register.
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Cortex-M3 Peripherals
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SPRUH22I – April 2012 – Revised November 2019
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