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SSI Registers
20.5.2.3 SSIDR Register (Offset = 8h) [reset = 0h]
SSIDR is shown in
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Summary
SSI Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit
Field
31-16
RESERVED
15-0
DATA
1426
M3 Synchronous Serial Interface (SSI)
Figure 20-12
and described in
Table.
Figure 20-12. SSIDR Register
R-0h
Table 20-6. SSIDR Register Field Descriptions
Type
Reset
R
0h
R/W
0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table
20-6.
9
Description
Reserved
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A
write operation writes the transmit FIFO.Software
must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are
ignored by the transmit logic. The receive logic automatically
right-justifies the data.
Reset type: PER.RESET
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
7
6
5
4
3
2
DATA
R/W-0h
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