Interrupts And Errors; Initialization And Configuration; Module Initialization; Configuring A Memory-To-Memory Transfer - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description

16.3.10 Interrupts and Errors

When a µDMA transfer is complete, the µDMA controller generates a completion interrupt on the interrupt
vector of the peripheral. Therefore, if µDMA is used to transfer data for a peripheral and interrupts are
used, then the interrupt handler for that peripheral must be designed to handle the µDMA transfer
completion interrupt. If the transfer uses the software µDMA channel, then the completion interrupt occurs
on the dedicated software µDMA interrupt vector (see
When µDMA is enabled for a peripheral, the µDMA controller stops the normal transfer interrupts for a
peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt
registers). Thus, when a large amount of data is transferred using µDMA, instead of receiving multiple
interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the
transfer is complete. Unmasked peripheral error interrupts continue to be sent to the interrupt controller.
If the µDMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it disables the µDMA channel that caused the error and generates an interrupt on the µDMA error
interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register to determine if
an error is pending. The ERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to
the ERRCLR bit.
Table 16-6 shows the dedicated interrupt assignments for the µDMA controller.

16.4 Initialization and Configuration

16.4.1 Module Initialization

Before the µDMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. Enable the µDMA peripheral in the System Control block. To do this, set the UDMA bit of the Run
Mode Clock Gating Control Register 2 (RCGC2) register.
2. Enable the µDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the DMA
Channel Control Base Pointer (DMACTLBASE) register. The base address must be aligned on a 1024-
byte boundary.

16.4.2 Configuring a Memory-to-Memory Transfer

µDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used for
software-initiated, memory-to-memory transfer if the associated peripheral is not being used.
16.4.2.1 Configure the Channel Attributes
Follow these steps to configure the channel attributes:
1. Program bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary
channel control structure for this transfer.
3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the µDMA
controller to respond to single and burst requests.
4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the µDMA
1164
M3 Micro Direct Memory Access ( µDMA)
Table 16-6. µDMA Interrupt Assignments
Interrupt
46
47
Copyright © 2012–2019, Texas Instruments Incorporated
Table 16-6).
Assignment
µDMA Software Channel Transfer
µDMA Error
SPRUH22I – April 2012 – Revised November 2019
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