C28 To M3 Core Ipc Status (Ctomipcsts) Register; C28 To M3 Core Ipc Status (Ctomipcsts) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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System Control Registers
Table 1-173. M3 to C28 Core IPC Acknowledge (CTOMIPCACK) Register Field Descriptions (continued)
Bit
Field
5
IPC6
4
IPC5
3
IPC4
2
IPC3
1
IPC2
0
IPC1

1.13.11.5 C28 to M3 Core IPC Status (CTOMIPCSTS) Register

31
30
IPC32
IPC31
R-0
R-0
23
22
IPC24
IPC23
R-0
R-0
15
14
IPC16
IPC15
R-0
R-0
7
6
IPC8
IPC7
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-174. C28 to M3 Core IPC Status (CTOMIPCSTS) Register Field Descriptions
Bit
Field
31
IPC32
30
IPC31
29
IPC30
28
IPC29
27
IPC28
278
System Control and Interrupts
Value
Description
0
CTOMIPCACK Flag 6. C28 to M3 core IPC flag 6 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
0
CTOMIPCACK Flag 5. C28 to M3 core IPC flag 5 acknowledge. Writing a '1' to this bit clears the
corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the CTOMIPCFLG and STS registers.
0
CTOMIPCACK Interrupt 4. C28 to M3 IPC interrupt 4 acknowledge. Writing a '1' to this bit clears
the corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not
readable in this register – it is readable in the CTOMIPCFLG and STS registers.
0
CTOMIPCACK Interrupt 3. C28 to M3 IPC interrupt 3 acknowledge. Writing a '1' to this bit clears
the corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not
readable in this register – it is readable in the CTOMIPCFLG and STS registers.
0
CTOMIPCACK Interrupt 2. C28 to M3 IPC interrupt 2 acknowledge. Writing a '1' to this bit clears
the corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not
readable in this register – it is readable in the CTOMIPCFLG and STS registers.
0
CTOMIPCACK Interrupt 1. C28 to M3 IPC interrupt 1 acknowledge. Writing a '1' to this bit clears
the corresponding bit in CTOMIPCFLG and CTOMIPCSTS to '0'. The status of this bit is not
readable in this register – it is readable in the CTOMIPCFLG and STS registers.
Figure 1-162. C28 to M3 Core IPC Status (CTOMIPCSTS) Register
29
28
IPC30
IPC29
R-0
R-0
21
20
IPC22
IPC21
R-0
R-0
13
12
IPC14
IPC13
R-0
R-0
5
4
IPC6
IPC5
R-0
R-0
Value
Description
0
CTOMIPCSTS Flag 32. C28 to M3 core IPC flag 32 status. The bit is '1' if the corresponding
CTOMIPCSET bit has been written with a '1' and CTOMIPCCLR or CTOMIPCACK bit has not been
written with a '1."
0
CTOMIPCSTS Flag 31. C28 to M3 core IPC flag 31 status. The bit is '1' if the corresponding
CTOMIPCSET bit has been written with a '1' and CTOMIPCCLR or CTOMIPCACK bit has not been
written with a '1."
0
CTOMIPCSTS Flag 30. C28 to M3 core IPC flag 30 status. The bit is '1' if the corresponding
CTOMIPCSET bit has been written with a '1' and CTOMIPCCLR or CTOMIPCACK bit has not been
written with a '1."
0
CTOMIPCSTS Flag 29. C28 to M3 core IPC flag 29 status. The bit is '1' if the corresponding
CTOMIPCSET bit has been written with a '1' and CTOMIPCCLR or CTOMIPCACK bit has not been
written with a '1."
0
CTOMIPCSTS Flag 28. C28 to M3 core IPC flag 28 status. The bit is '1' if the corresponding
CTOMIPCSET bit has been written with a '1' and CTOMIPCCLR or CTOMIPCACK bit has not been
written with a '1."
Copyright © 2012–2019, Texas Instruments Incorporated
27
26
IPC28
IPC27
R-0
R-0
19
18
IPC20
IPC19
R-0
R-0
11
10
IPC12
IPC11
R-0
R-0
3
2
IPC4
IPC3
R-0
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25
24
IPC26
IPC25
R-0
R-0
17
16
IPC18
IPC17
R-0
R-0
9
8
IPC10
IPC9
R-0
R-0
1
0
IPC2
IPC1
R-0
R-0
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