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15
7
6
Reserved
DCBEVT2
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
15- 7
Reserved
6
DCBEVT2
5
DCBEVT1
4
DCAEVT2
3
DCAEVT1
2
OST
1
CBC
0
Reserved
Figure 7-116. Trip-Zone Digital Compare Event Select Register (TZDCSEL)
15
12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Figure 7-115. Trip-Zone Force Register (TZFRC)
5
4
DCBEVT1
DCAEVT2
R/W-0
R/W-0
Table 7-65. Trip-Zone Force Register (TZFRC) Field Descriptions
Value
Description
Reserved
Force Flag for Digital Compare Output B Event 2
0
Writing 0 has no effect. This bit always reads back 0.
1
Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit.
Force Flag for Digital Compare Output B Event 1
0
Writing 0 has no effect. This bit always reads back 0.
1
Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit.
Force Flag for Digital Compare Output A Event 2
0
Writing 0 has no effect. This bit always reads back 0.
1
Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit.
Force Flag for Digital Compare Output A Event 1
0
Writing 0 has no effect. This bit always reads back 0
1
Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit.
Force a One-Shot Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a one-shot trip event and sets the TZFLG[OST] bit.
Force a Cycle-by-Cycle Trip Event via Software
0
Writing of 0 is ignored. Always reads back a 0.
1
Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.
Reserved
11
9
DCBEVT2
R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3
2
DCAEVT1
OST
R/W-0
R/W-0
8
6
5
DCBEVT1
DCAEVT2
R/W-0
C28 Enhanced Pulse Width Modulator (ePWM) Module
1
CBC
Reserved
R/W-0
3
2
DCAEVT1
R/W-0
R/W-0
Registers
8
0
R- 0
0
765
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