Ecap Control Register 2 (Ecctl2) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 8-7. ECAP Control Register 1 (ECCTL1) Field Descriptions (continued)
Bit(s) Field
8 CAPLDEN
7 CTRRST4
6 CAP4POL
5 CTRRST3
4 CAP3POL
3 CTRRST2
2 CAP2POL
1 CTRRST1
0 CAP1POL
15
7 6
SYNCO_SEL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value Description
00100 Divide by 8
00101 Divide by 10
...
11110 Divide by 60
11111 Divide by 62
Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not
disable CEVTn events from being generated.
0 Disable CAP1-4 register loads at capture event time.
1 Enable CAP1-4 register loads at capture event time.
Counter Reset on Capture Event 4
0 Do not reset counter on Capture Event 4 (absolute time stamp operation)
1 Reset counter after Capture Event 4 time-stamp has been captured
(used in difference mode operation)
Capture Event 4 Polarity select
0 Capture Event 4 triggered on a rising edge (RE)
1 Capture Event 4 triggered on a falling edge (FE)
Counter Reset on Capture Event 3
0 Do not reset counter on Capture Event 3 (absolute time stamp)
1 Reset counter after Event 3 time-stamp has been captured
(used in difference mode operation)
Capture Event 3 Polarity select
0 Capture Event 3 triggered on a rising edge (RE)
1 Capture Event 3 triggered on a falling edge (FE)
Counter Reset on Capture Event 2
0 Do not reset counter on Capture Event 2 (absolute time stamp)
1 Reset counter after Event 2 time-stamp has been captured
(used in difference mode operation)
Capture Event 2 Polarity select
0 Capture Event 2 triggered on a rising edge (RE)
1 Capture Event 2 triggered on a falling edge (FE)
Counter Reset on Capture Event 1
0 Do not reset counter on Capture Event 1 (absolute time stamp)
1 Reset counter after Event 1 time-stamp has been captured (used in difference mode
operation)
Capture Event 1 Polarity select
0 Capture Event 1 triggered on a rising edge (RE)
1 Capture Event 1 triggered on a falling edge (FE)
Figure 8-18. ECAP Control Register 2 (ECCTL2)
Reserved
R-0
5 4
SYNCI_EN TSCTRSTOP
R/W-0 R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
Capture Module - Control and Status Registers
11 10
APWMPOL
R/W-0
3 2
REARM STOP_WRAP
R/W-0 R/W-1
C28 Enhanced Capture (eCAP) Module
9 8
CAP/APWM SWSYNC
R/W-0 R/W-0
1 0
CONT/ONESH
T
R/W-1 R/W-0
803