Adc Interrupt Trigger Soc Select 2 Register (Adcintsocsel2) (Address Offset 15H); Adc Soc Flag 1 Register (Adcsocflg1) (Address Offset 18H); Adc Soc Force 1 Register (Adcsocfrc1) (Address Offset 1Ah); Adc Interrupt Trigger Soc Select 2 Register (Adcintsocsel2) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 10-31. ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) (Address Offset 15h)
15
14
13
12
SOC15
SOC14
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-16. ADC Interrupt Trigger SOC Select 2 Register (ADCINTSOCSEL2) Field Descriptions
Bit
Field
15-0
SOCx
(x = 15 to 8)
Figure 10-32. ADC SOC Flag 1 Register (ADCSOCFLG1) (Address Offset 18h)
15
14
SOC15
SOC14
R-0
R-0
7
6
SOC7
SOC6
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-17. ADC SOC Flag 1 Register (ADCSOCFLG1) Field Descriptions
Bit
Field
15-0
SOCx
(x = 15 to 0)
Figure 10-33. ADC SOC Force 1 Register (ADCSOCFRC1) (Address Offset 1Ah)
15
14
SOC15
SOC14
R/W-0
R/W-0
7
6
SOC7
SOC6
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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11
10
9
SOC13
SOC12
R/W-0
R/W-0
Value
Description
SOCx ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOCx. This field
overrides the TRIGSEL field in the ADCSOCxCTL register.
00
No ADCINT will trigger SOCx. TRIGSEL field determines SOCx trigger.
01
ADCINT1 will trigger SOCx. TRIGSEL field is ignored.
10
ADCINT2 will trigger SOCx. TRIGSEL field is ignored.
11
Invalid selection.
13
12
SOC13
SOC12
R-0
R-0
5
4
SOC5
SOC4
R-0
R-0
Value
Description
SOCx Start of Conversion Flag. Indicates the state of individual SOC conversions.
0
No sample pending for SOCx.
1
Trigger has been received and sample is pending for SOCx.
The bit will be automatically cleared when the respective SOCx conversion is started. If contention
exists where this bit receives both a request to set and a request to clear on the same cycle,
regardless of the source of either, this bit will be set and the request to clear will be ignored. In this
case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this
bit was previously set or not.
13
12
SOC13
SOC12
R/W-0
R/W-0
5
4
SOC5
SOC4
R/W-0
R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
8
7
6
5
SOC11
SOC10
R/W-0
R/W-0
11
10
SOC11
SOC10
R-0
R-0
3
2
SOC3
SOC2
R-0
R-0
11
10
SOC11
SOC10
R/W-0
R/W-0
3
2
SOC3
SOC2
R/W-0
R/W-0
Analog-to-Digital Converter (ADC)
4
3
2
1
SOC9
SOC8
R/W-0
R/W-0
9
8
SOC9
SOC8
R-0
R-0
1
0
SOC1
SOC0
R-0
R-0
9
8
SOC9
SOC8
R/W-0
R/W-0
1
0
SOC1
SOC0
R/W-0
R/W-0
Analog Subsystem
0
883

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