Usb Transmit Control And Status Endpoint N High Register (Usbtxcsrh[1]- Usbtxcsrh[15]); Usb Transmit Control And Status Endpoint N High Register (Usbtxcsrh[N]) In Otg A/Host Mode; Usb Transmit Control And Status Endpoint N High Register (Usbtxcsrh[N]) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions
18.5.35 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-
USBTXCSRH[15])
The USB transmit control and status endpoint n high 8-bit registers (USBTXCSRH[n]) provide additional
control for transfers through the currently selected transmit endpoint.
For the specific offset for each register see
Mode(s): OTG A or Host
The USBTXCSRH[n] registers in OTG A/Host Mode are shown in
46.
Figure 18-43. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
7 6
AUTOSET Reserved
R/W-0 R-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-46. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n])
Bit Field Value
7 AUTOSET
0
1
6 Reserved 0
5 MODE
0
1
4 DMAEN
0
1
3 FDT
0
1
2 DMAMOD
0
1
1 DTWE
0
1
1342
M3 Universal Serial Bus (USB) Controller
Table
OTG B or Device
in OTG A/Host Mode
5 4
MODE DMAEN
R/W-0 R/W-0
in OTG A/Host Mode Field Descriptions
Description
Auto Set
The TXRDY bit must be set manually.
Enables the TXRDY bit to be automatically set when data of the maximum packet size (value in
USBTXMAXP[n]) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is
loaded, then the TXRDY bit must be set manually.
Reserved
Mode
Note: This bit only has an effect when the same endpoint FIFO is used for both transmit and receive
transactions.
Enables the endpoint direction as RX.
Enables the endpoint direction as TX.
DMA Request Enable
Note: Three TX and three /RX endpoints can be connected to the μDMA module. If this bit is set for a
particular endpoint, the DMAATX, DMABTX, or DMACTX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
Disables the μDMA request for the transmit endpoint.
Enables the μDMA request for the transmit endpoint.
Force Data Toggle
No effect
Forces the endpoint DT bit to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received. This bit can be used by interrupt transmit endpoints that are used to
communicate rate feedback for isochronous endpoints.
Note: This bit should only be set when the TXRDY bit is set. At other times, it may cause data to be
corrupted.
DMA Request Mode
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
An interrupt is generated after every μDMA packet transfer.
An interrupt is generated only after the entire μDMA transfer is complete.
Note: This bit is valid only when the endpoint is operating in Bulk or Interrupt mode.
Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
The DT bit cannot be written.
Enables the current state of the transmit endpoint data to be written (see DT bit).
Copyright © 2012–2019, Texas Instruments Incorporated
18-4.
Figure 18-43
3 2
FDT DMAMOD
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
and described in Table 18-
1 0
DTWE DT
R/W-0 R/W-0
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