Host Bus Mode; Control Pins; Sdram Write Cycle - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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(EPI0S [17:16])

(EPI0S [15:0])

AD [15:0]drivenout

17.7 Host Bus Mode

The host bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051 devices and

SRAM devices. This interface is asynchronous and uses strobe pins to control activity. Addressable

memory can be doubled using Host Bus-16 mode as it performs half-word accesses. EPI0S0 should be

connected to A0 of 16-bit memories.

The main three strobes are Address Latch Enable (ALE), Write (WR), and Read (RD, sometimes called

OE). Note that the timings are designed for older logic and so are hold-time vs. setup-time specific. The

polarity of the read and write strobes can be active High or active Low by clearing or setting the RDHIGH

and WRHIGH bits in the EPI Host-Bus n Configuration (EPIHBnCFGn) register.

The ALE can be changed to an active-low chip select signal, CS, through the EPIHBnCFGn register. The

ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared. All Host-Bus

accesses have an address phase followed by a data phase. The ALE indicates to an external latch to

capture the address then hold it until the data phase. The polarity of the ALE can be active High or Low by

clearing or setting the ALEHIGH bit in the EPI Host-Bus n Configuration (EPIHBnCFGn) register. CS is

best used for Host-Bus unmuxed mode in which EPI address and data pins are separate. The CS

indicates when the address and data phases of a read or write access are occurring. Both the ALE and

the CS modes can be enhanced to access four external devices using settings in the EPIHBnCFGn

the EPIHBnCFGn register. Additionally, within these wait state options, the WRWSM and RDWSM bit of

the EPIHBnTIMEn register can be set to reduce the given wait states by 1 EPI clock cycle for finer

granularity.

For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and output

to what the XFIFO can handle.

SPRUH22I – April 2012 – Revised November 2019

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Figure 17-4. SDRAM Write Cycle

AD [15:0]drivenout

External Peripheral Interface (EPI)

Host Bus Mode

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