Configuring A Peripheral For Simple Transmit; Channel Control Structure Offsets For Channel 30; Channel Control Word Configuration For Memory Transfer Example - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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controller to recognize requests for this channel.
16.4.2.2 Configure the Channel Control Structure
After configuring the channel attributes, the channel control structure must be configured.
This example transfers 256 words from one memory buffer to another. Channel 30 is used for a software
transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control table. The
channel control structure for channel 30 is located at the offsets shown in
Control Table Base + 0x1E0
Control Table Base + 0x1E4
Control Table Base + 0x1E8
16.4.2.2.1 Configure the Source and Destination
Now set the source and destination end pointers to the last address for the transfer (inclusive).
1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC.
2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer + 0x3FC.
The control word at offset 0x1E8 must be programmed according to
Table 16-8. Channel Control Word Configuration for Memory Transfer Example
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
Reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
16.4.2.3 Start the Transfer
The channel is configured and is now ready to start.
1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register.
2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ)
register.
The µDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt when the
transfer is complete. If needed, the status can be checked by reading bit 30 of the DMAENASET register.
This bit is automatically cleared when the transfer is complete. The status can also be checked by reading
the XFERMODE field of the channel control word at offset 0x1E8. This field is automatically cleared at the
end of the transfer.

16.4.3 Configuring a Peripheral for Simple Transmit

This example configures the µDMA controller to transmit a buffer of data to a peripheral. The peripheral
has a transmit FIFO with a trigger level of 4. The example peripheral uses µDMA channel 7.
SPRUH22I – April 2012 – Revised November 2019
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Table 16-7. Channel Control Structure Offsets for Channel 30
Offset
Bits
31:30
29:28
27:26
25:24
23:18
17:14
13:4
3
2:0
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Initialization and Configuration
Table 16-7.
Description
Channel 30 Source End Pointer
Channel 30 Destination End Pointer
Channel 30 Control Word
Table 16-8.
Value Description
32-bit destination address
2
increment
2 32-bit destination data size
32-bit source address
2
increment
2 32-bit source data size
0 Reserved
3 Arbitrates after 8 transfers
255 Transfer 256 items
0 N/A for this transfer type
Use Auto-request transfer
2
mode
M3 Micro Direct Memory Access ( µDMA)
1165