Master Receive With Repeated Start - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
Idle
Write Slave
Address and
Receive Bit
to I2CMSA
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write 1011
to I2CMCS
1494
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-10. Master RECEIVE with Repeated START
Sequence
may be
omitted in a
Single Master
system
Write 1001
to I2CMCS
Error Service
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Read I2CMCS
BUSY bit=0?
NO
YES
NO
ERROR bit=0?
Read data from
I2CMDR
NO
Index=m-1?
YES
Write 0101
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
NO
ARBLST bit=1?
YES
Write 100
to I2CMCS
Error Service
Idle
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