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14.1.1 Features
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
•
One 16-byte receive FIFO and one 16-byte transmit FIFO
•
One interrupt that can always be used by the CPU. This interrupt can be generated as a result of one
of the following conditions: transmit-data ready, receive-data ready, register-access ready, no-
acknowledgment received, arbitration lost, stop condition detected, addressed as slave.
•
An additional interrupt that can be used by the CPU when in FIFO mode
•
Module enable/disable capability
•
Free data format mode
14.1.2 Features Not Supported
The I2C module does not support:
•
High-speed mode (Hs-mode)
•
CBUS-compatibility mode
14.1.3 Functional Overview
Each device connected to an I2C-bus is recognized by a unique address. Each device can operate as
either a transmitter or a receiver, depending on the function of the device. A device connected to the I2C-
bus can also be considered as the master or the slave when performing data transfers. A master device is
the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer.
During this transfer, any device addressed by this master is considered a slave. The I2C module supports
the multi-master mode, in which one or more devices capable of controlling an I2C-bus can be connected
to the same I2C-bus.
For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL), as
shown in
Figure
14-2. These two pins carry information between the 28x device and other devices
connected to the I2C-bus. The SDA and SCL pins both are bidirectional. They each must be connected to
a positive supply voltage using a pull-up resistor. When the bus is free, both pins are high. The driver of
these two pins has an open-drain configuration to perform the required wired-AND function.
There are two major transfer techniques:
•
Standard Mode: Send exactly n data values, where n is a value you program in an I2C module
register. See
Table 14-5
•
Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new
START condition. See
.
The I2C module consists of the following primary blocks:
•
A serial interface: one data pin (SDA) and one clock pin (SCL)
•
Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the
SDA pin and the CPU
•
Control and status registers
•
A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
for register information.
Table 14-5
for RM bit information.
Copyright © 2012–2019, Texas Instruments Incorporated
Introduction to the I2C Module
C28 Inter-Integrated Circuit Module
1009
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