I2C Module Registers - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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forced to their default values, and the I2C module remains disabled until IRS is changed to 1. The SDA

and SCL pins are in the high-impedance state.

Initiate a device reset by driving the XRS pin low. The entire device is reset and is held in the reset

state until you drive the pin high. When XRS is released, all I2C module registers are reset to their

default values. The IRS bit is forced to 0, which resets the I2C module. The I2C module stays in the

reset state until you write 1 to IRS.

IRS must be 0 while you configure/reconfigure the I2C module. Forcing IRS to 0 can be used to save

power and to clear error conditions.

14.5 I2C Module Registers

lists the I2C module registers. All but the receive and transmit shift registers (I2CRSR and

I2CXSR) are accessible to the CPU.

NOTE: To use the I2C module the system clock to the module must be enabled by setting the

appropriate bit in the PCLKR0 register. See TMS320x2833x, 2823x device System Control

and Interrupts Reference Guide (literature number SPRUFB0).

SPRUH22I – April 2012 – Revised November 2019

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Table 14-4. I2C Module Registers

I2C own address register

I2C interrupt enable register

I2C status register

I2C clock low-time divider register

I2C clock high-time divider register

I2C data count register

I2C data receive register

I2C slave address register

I2C data transmit register

I2C mode register

I2C interrupt source register

I2C extended mode register

I2C prescaler register

I2C FIFO transmit register

I2C FIFO receive register

I2C receive shift register (not accessible to the CPU)

I2C transmit shift register (not accessible to the CPU)

C28 Inter-Integrated Circuit Module

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