C28 User_Swreg1 Register; C28_User_Swreg2 Register; Missing Clock Reference Limit (Mclklimit) Register Field Descriptions; C28 User_Swreg1 Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 1-101. Missing Clock Reference Limit (MCLKLIMIT) Register Field Descriptions

REFCLKHILIMIT

REFCLKLOLIMIT

NOTE: Due to the asynchronous nature of the missing clock detect block, the MCLKDETEN = 0 write will

take 3 cycles (2 cycles best case) for the 10MHZ clock to generate the synchronized reset for the internal

counters. Hence if MCLKDETEN = 0 and REFCLKHILIMIT/REFCLKLOLIMIT values are set back to back,

then MCLKDETEN = 0, will not propagate to the counters. As a result, the new

REFCLKHILIMIT/REFCLKLOLIMIT values will take effect and may generate a missing_clock condition.

This can be avoided by adding three empty cycles between setting MCLKDETEN = 0 and setting the

REFCLKHILIMIT and REFCLKLOLIMIT values.

1.13.6.7 C28 USER_SWREG1 Register

This register is used by the PIE mismatch handler in C-Boot ROM as mentioned in the safety features

section of this chapter. The user should initialize this register with the lower 16 bits of the application PIE

mismatch handler address. If the user doesn't wish to install a PIE mismatch handler, this register is to be

left at its reset value.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

This register is used by the PIE mismatch handler in C-Boot ROM as mentioned in the safety features

section of this chapter. The user should initialize the lower 8 bits of this register with the upper 8 bits of the

application PIE mismatch handler address (note that on the C28x addresses are limited to 22 bits). If the

user does not wish to install a PIE mismatch handler then this register is to be left at its reset value.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUH22I – April 2012 – Revised November 2019

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Reference Clock High Limit

Contains the higher limit for the reference clock counter.

Reference Clock Low Limit

Contains the lower limit for the reference clock counter.

Figure 1-91. C28 USER_SWREG1 Register

Table 1-102. C28 USER_SWREG1 Register Field Descriptions

General purpose register for C28 software use.

Figure 1-92. C28_USER_SWREG2 Register

Table 1-103. C28_USER_SWREG2 Register Field Descriptions

General purpose register for C28 software use.

System Control Registers

System Control and Interrupts

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