Time-Base Control Register 2 (Tbctl2); Epwmx Link Register (Epwmxlink); Time-Base Control Register 2 (Tbctl2) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 7-34. High-Resolution Period Control Register (HRPCTL) Field Descriptions (continued)
Bit Field
2 TBPHSHRLOADE
1 Reserved
0 HRPE
15 14
PRDLDSYNC
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-35. Time-Base Control Register 2 (TBCTL2) Field Descriptions
Bit Field
15-14 PRDLDSYNC
13-0 Reserved
31
15 12
CMPCLINK
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value Description
TBPHSHR Load Enable
This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN,
TBCTL[SWFSYNC], or digital compare event. This allows for multiple ePWM modules
operating at the same frequency to be phase aligned with high-resolution.
0 Disables synchronization of high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital
compare event.
1 Synchronize the high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital
comparator synchronization event. The phase is synchronized using the contents of the high-
resolution phase TBPHSHR register.
The TBCTL[PHSEN] bit which enables the loading of the TBCTR register with TBPHS register
value on a SYNCIN, or TBCTL[SWFSYNC] event works independently. However, users need
to enable this bit also if they want to control phase in conjunction with the high-resolution
period feature.
Note: This bit and the TBCTL[PHSEN] bit must be set to 1 when high resolution period control
is enabled for up-down count mode even if TBPHSHR = 0x00.
Reserved
High Resolution Period Enable Bit
0 High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM.
1 High resolution period enabled. In this mode the HRPWM module can control high-resolution
of both the duty and frequency.
When high-resolution period is enabled, TBCTL[CTRMODE] = 0,1 (down-count mode) is not
supported.
Figure 7-85. Time-Base Control Register 2 (TBCTL2)
13
Value Description
Shadow to Active Period Register Load on SYNC Event
00 Shadow to Active Load of TBRD occurs only when TBCTR = 0 (same as legacy).
01 Shadow to Active Load of TBRD occurs both when TBCTR = 0 and when SYNC occurs.
10 Shadow to Active Load of TBPRD occurs only when a SYNC is received.
11 Reserved
Note: This bit selection is valid only if TBCTL[PRDLD]=0.
Reserved
Figure 7-86. EPWMx Link Register (EPWMXLINK)
Reserved
11
CMPBLINK
R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
CMPALINK
R/W-0
C28 Enhanced Pulse Width Modulator (ePWM) Module
Registers
20 19
CMPDLINK
R/W-0
4 3
TBPRDLINK
R/W-0
0
16
0
739