Functional Description; Transmit/Receive Logic; Uart Module Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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System Clock

Identification

UARTPCellID0

UARTPCellID1

UARTPCellID2

UARTPCellID3

UARTPeriphID0

UARTPeriphID1

UARTPeriphID2

UARTPeriphID3

UARTPeriphID4

UARTPeriphID5

UARTPeriphID6

UARTPeriphID7

21.3 Functional Description

Each UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in

functionality to a 16C550 UART, but is not register-compatible.

The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control

(UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are

programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is

disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping.

The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an

infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the

UARTCTL register.

The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The

control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first),

parity bit, and the stop bits according to the programmed configuration in the control registers. See

for details.

SPRUH22I – April 2012 – Revised November 2019

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Figure 21-1. UART Module Block Diagram

Interrupt Control

Control/Status

M3 Universal Asynchronous Receivers/Transmitters (UARTs)

Functional Description

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