Dma Channel Primary Alternate Clear (Dmaaltclr), Offset 0X034; Dma Channel Priority Set (Dmaprioset), Offset 0X038; Dma Channel Priority Clear (Dmaprioclr), Offset 0X03C; Dma Channel Primary Alternate Clear (Dmaaltclr) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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16.7.14 DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034

Each bit of the DMAALTCLR register represents the corresponding µDMA channel. Setting a bit clears the
corresponding SET[n] bit in the DMAALTSET register.
Figure 16-23. DMA Channel Primary Alternate Clear (DMAALTCLR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-30. DMA Channel Primary Alternate Clear (DMAALTCLR) Register Field Descriptions
Bit Field
31-0 CLR[n]

16.7.15 DMA Channel Priority Set (DMAPRIOSET), offset 0x038

Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to have a high priority level. Reading the register returns the status of the
channel priority mask.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-31. DMA Channel Priority Set (DMAPRIOSET) Register Field Descriptions
Bit Field
31-0 SET[n]

16.7.16 DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C

Each bit of the DMAPRIOCLR register represents the corresponding µDMA channel. Setting a bit clears
the corresponding SET[n] bit in the DMAPRIOSET register.
Figure 16-25. DMA Channel Priority Clear (DMAPRIOCLR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Channel [n] Alternate Clear
Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these
bits to select the alternate channel control data structure.
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel
[n] is using the primary control structure.
Figure 16-24. DMA Channel Priority Set (DMAPRIOSET) Register
Value Description
Channel [n] Priority Set
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAPRIOCLR register.
0 μDMA channel [n] is using the default priority level.
1 μDMA channel [n] is using a high priority level.
Copyright © 2012–2019, Texas Instruments Incorporated
CLR[n]
W
SET[n]
R/W-0
CLR[n]
W
M3 Micro Direct Memory Access ( µDMA)
µDMA Register Descriptions
0
0
0
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