Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Figure 7-29. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on
TBCTR
EPWMxA
Z
EPWMxB
A PWM period = 2 × TBPRD × TBCLK
B Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement
techniques.
C Duty modulation for EPWMxA is set by CMPA and CMPB.
D Low time duty for EPWMxA is proportional to (CMPA + CMPB).
E To change this example to active high, CMPA and CMPB actions need to be inverted (i.e., Set ! Clear and Clear Set).
F Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB)
Example 7-6 contains a code sample showing initialization and run time for the waveforms in
Use the code in Example 7-5
Example 7-6. Code Sample for
// Initialization Time
// = = = = = = = = = = = = = = = = = = = = = = = =
EPwm1Regs.TBPRD = 600;
EPwm1Regs.CMPA.half.CMPA = 250;
EPwm1Regs.CMPB = 450;
EPwm1Regs.TBPHS = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; //
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CBD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.PRD = AQ_SET;
// Run Time
// = = = = = = = = = = = = = = = = = = = = = = = =
EPwm1Regs.CMPA.half.CMPA = EdgePosA;
EPwm1Regs.CMPB = EdgePosB;
SPRUH22I – April 2012 – Revised November 2019
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EPWMxA—Active Low
CA
CB
P
to define the headers.
Figure 7-29
Copyright © 2012–2019, Texas Instruments Incorporated
CA
Z
// Period = 2 ´ 600 TBCLK counts
// Compare A = 250 TBCLK counts
// Compare B = 450 TBCLK counts
// Set Phase register to zero
// clear TB counter
Symmetric
// Phase loading disabled
// TBCLK = SYSCLKOUT
// load on CTR = Zero
// load on CTR = Zero
// adjust duty for output EPWM1A only
C28 Enhanced Pulse Width Modulator (ePWM) Module
ePWM Submodules
CB
P
Figure 7-29.
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