Epi Dma Transmit Count (Epidmatxcnt) Register, Offset 0X208; Epi Dma Transmit Count (Epidmatxcnt) Register [Offset 0X208]; Epi Interrupt Mask (Epiim) Register, 0X210; Epi Interrupt Mask (Epiim) Register [Offset 0X210] - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

17.11.20 EPI DMA Transmit Count (EPIDMATXCNT) Register, offset 0x208

This register is used to program the total number of transfers (byte, halfword or word) by the µDMA to
WRFIFO. As each transfer is processed by the EPI, the TXCNT bit field value is decreased by 1. When
TXCNT = 0, the EPI's uDMA request signal is de-asserted
Figure 17-47. EPI DMA Transmit Count (EPIDMATXCNT) Register [offset 0x208]
31
Reserved
R-0x0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-33. EPI DMA Transmit Count (EPIDMATXCNT) Register Field Descriptions
Bit Field
31-16 Reserved
15-0 TXCNT

17.11.21 EPI Interrupt Mask (EPIIM) Register, 0x210

This register is the interrupt mask set or clear register. For each interrupt source (read, write, and error), a
mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller; a mask value
of 0 prevents the interrupt source from triggering an interrupt.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-34. EPI Interrupt Mask (EPIIM) Register Field Descriptions
Bit Field
31-5 Reserved
4 DMAWRIM
3 DMARDIM
2 WRIM
1 RDIM
1258
External Peripheral Interface (EPI)
16 15
Value Description
Reserved
DMA Count
This field is used to program the total number of transfers (byte, halfword or word) from the µDMA
to the EPI WRFIFO.
Figure 17-48. EPI Interrupt Mask (EPIIM) Register [offset 0x210]
Reserved
R-0x000
Value Description
Reserved
Write uDMA Interrupt Mask
0 DMAWRRIS in the EPIRIS register is masked and does not cause an interrupt
1 DMAWRRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt
controller
Read uDMA Interrupt Mask
0 DMARDRIS in the EPIRIS register is masked and does not cause an interrupt
1 DMARDRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt
controller
Write Interrupt Mask
0 WRRIS in the EPIRIS register is masked and does not cause an interrupt.
1 WRRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
Read Interrupt Mask
0 RDRIS in the EPIRIS register is masked and does not cause an interrupt.
1 RDRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0x000
5
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
3
TXCNT
R/W-000
4 3 2 1
DMAW DMAR WRIM RDIM
RIM DIM
R/W-0 R/W-0 R/W-0 R/W-0
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0
16
0
ERRI
M
R/W-0