Table of Contents
Advertisement
www.ti.com
4.2
C28 General-Purpose Input/Output (GPIO)
4.2.1 Introduction
The GPIO multiplexing (MUX) registers are used to select the operation of shared pins. The pins are
named by their general purpose I/O name (i.e., GPIO0). These pins can be individually selected to
operate as digital I/O, referred to as GPIO, or connected to one of up to three peripheral I/O signals (via
the GPxMUXn registers). If selected for digital I/O mode, registers are provided to configure the pin
direction (via the GPxDIR registers). You can also qualify the input signals to remove unwanted noise (via
the GPxQSELn and GPxCTRL registers).
4.2.2 GPIO Module Overview
Up to three independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to
individual pin bit-I/O capability. There are six I/O ports:
•
Port A consists of GPIO0-GPIO31
•
Port B consists of GPIO32-GPIO63
•
Port C consists of GPIO68-GPIO71
•
Port E consists of GPIO128-GPIO135
•
Analog Port 1 consists of AI00-AI015
•
Analog Port 2 consists of AIO16-AIO31
Figure 4-35
through
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 4-38
shows the basic modes of operation for the GPIO module.
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
General-Purpose Input/Output (GPIO)
369
Advertisement
Chapters
Table of Contents
