Table of Contents
Advertisement
www.ti.com
24.4.4.3 Link Register (LR)
The link register (LR) is register R14, and it stores the return information for subroutines, function calls,
and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-0
LINK
24.4.4.4 Program Counter (PC)
The program counter (PC) is register R15, and it contains the current program address. On reset, the
processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the
reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be
accessed in either privileged or unprivileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-0
PC
24.4.4.5 Program Status Register (PSR)
The program status register (PSR) has three functions, and the register bits are assigned to the different
functions:
•
Application Program Status Register (APSR), bits 31:27,
•
Execution Program Status Register (EPSR), bits 26:24, 15:10
•
Interrupt Program Status Register (IPSR), bits 6:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be
accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the
Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return
zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored.
Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted
(see
Section
24.7.7).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 24-5. Link Register
Table 24-5. Link Register Field Descriptions
Value
Description
Return address
Figure 24-6. Program Counter Register
Table 24-6. Program Counter Register Field Descriptions
Value
Description
Current program address
Copyright © 2012–2019, Texas Instruments Incorporated
Table 24-18
for the values and description.
LINK
R/W
PC
R/W
Programming Model
0
0
1573
Cortex-M3 Processor
Advertisement
Chapters
Table of Contents
