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Figure 14-12. Arbitration Procedure Between Two Master-Transmitters
Bus line
SCL
Data from
device #1
Data from
device #2
Bus line
SDA
14.3 Interrupt Requests Generated by the I2C Module
The I2C module can generate seven types of basic interrupt requests, which are described in
Section
14.3.1. Two of these can tell the CPU when to write transmit data and when to read receive data.
If you want the FIFOs to handle transmit and receive data, you can also use the FIFO interrupts described
in
Section
14.3.2. The basic I2C interrupts are combined to form PIE Group 8, Interrupt 1
(I2CINT1A_ISR), and the FIFO interrupts are combined to form PIE Group 8, Interrupt 2 (I2CINT2A_ISR).
14.3.1 Basic I2C Interrupt Requests
The I2C module generates the interrupt requests described in
requests are multiplexed through an arbiter to a single I2C interrupt request to the CPU. Each interrupt
request has a flag bit in the status register (I2CSTR) and an enable bit in the interrupt enable register
(I2CIER). When one of the specified events occurs, its flag bit is set. If the corresponding enable bit is 0,
the interrupt request is blocked. If the enable bit is 1, the request is forwarded to the CPU as an I2C
interrupt.
The I2C interrupt is one of the maskable interrupts of the CPU. As with any maskable interrupt request, if
it is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine
(I2CINT1A_ISR). The I2CINT1A_ISR for the I2C interrupt can determine the interrupt source by reading
the interrupt source register, I2CISRC. Then the I2CINT1A_ISR can branch to the appropriate subroutine.
After the CPU reads I2CISRC, the following events occur:
1. The flag for the source interrupt is cleared in I2CSTR. Exception: The ARDY, RRDY, and XRDY bits in
I2CSTR are not cleared when I2CISRC is read. To clear one of these bits, write a 1 to it.
2. The arbiter determines which of the remaining interrupt requests has the highest priority, writes the
code for that interrupt to I2CISRC, and forwards the interrupt request to the CPU.
I2C Interrupt Request
XRDYINT
RRDYINT
SPRUH22I – April 2012 – Revised November 2019
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1
0
1
0
1
0
Device #2 drives SDA
Table 14-3. Descriptions of the Basic I2C Interrupt Requests
Interrupt Source
Transmit ready condition: The data transmit register (I2CDXR) is ready to accept new data because the
previous data has been copied from I2CDXR to the transmit shift register (I2CXSR).
As an alternative to using XRDYINT, the CPU can poll the XRDY bit of the status register, I2CSTR.
XRDYINT should not be used when in FIFO mode. Use the FIFO interrupts instead.
Receive ready condition: The data receive register (I2CDRR) is ready to be read because data has been
copied from the receive shift register (I2CRSR) to I2CDRR.
As an alternative to using RRDYINT, the CPU can poll the RRDY bit of I2CSTR. RRDYINT should not
be used when in FIFO mode. Use the FIFO interrupts instead.
Copyright © 2012–2019, Texas Instruments Incorporated
Interrupt Requests Generated by the I2C Module
Device #1 loses arbitration
and switches off
0
1
0
0
1
0
Table
14-3. As shown in
C28 Inter-Integrated Circuit Module
1
1
Figure
14-13, all
1017
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