Ti Synchronous Serial Frame Format (Continuous Transfer); Freescale Spi Format (Single Transfer) With Spo=0 And Sph=0; Freescale Spi Format (Continuous Transfer) With Spo=0 And Sph=0 - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on each
falling edge of SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the
first rising edge of SSIClk after the LSB has been latched.
The figure below shows the Texas Instruments synchronous serial frame format when back-to-back
frames are transmitted.
Figure 20-3. TI Synchronous Serial Frame Format (Continuous Transfer)
20.3.4.1 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select.
The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are
programmable through the SPO and SPH bits in the SSICR0 control register.
20.3.4.1.1 SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state low value on the SSIClk pin. If
the SPO bit is set, a steady state high value is placed on the SSIClk pin when data is not being
transferred.
20.3.4.1.2 SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state. The
state of this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase control bit is clear, data is captured on
the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition.
20.3.4.2 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0
are shown in Figure 20-4
Figure 20-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
Figure 20-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
1414
M3 Synchronous Serial Interface (SSI)
SSIClk
SSIFss
SSITx/SSIRx MSB
and Figure 20-5
MSB
MSB
Note: Q is undefined.
SSIClk
SSIFss
SSIRx
LSB
MSB
SSITx LSB MSB
Copyright © 2012–2019, Texas Instruments Incorporated
LSB
4 to16 bits
4 to16 bits
LSB
4 to16 bits
LSB
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
LSB Q
LSB
MSB
MSB
Submit Documentation Feedback