Initialization And Configuration - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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22.4 Initialization and Configuration

The following example shows how to configure the I2C module to transmit a single byte as a master. This
assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control
chapter.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
chapter. To find out which GPIO port to enable, refer to the GPIOs chapter.
3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL
register (see the GPIOs chapter).
4. Enable the I2C pins for Open Drain operation. See the GPIOs chapter.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate pins.
See the GPIOs chapter.
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0010.
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value.
The value written to the I2CMTPR register represents the number of system clock periods in one SCL
clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
8. Specify the slave address of the master and that the next operation is a Transmit by writing the
I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the desired
data.
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register with a
value of 0x0000.0007 (STOP, START, RUN).
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has been
cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
To generate a single transmit cycle, the I2C Master Slave Address (I2CMSA) register is written with the
desired address, the R/S bit is cleared, and the I2C Master Control/Status (I2CMCS) register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), an interrupt becomes active and the data may be read
from the I2CMDR register.
When the I2C module operates in Master receiver mode, the ACK bit in the I2CMCS register is normally
set, causing the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must
be cleared when the I2C bus controller requires no further data to be transmitted from the slave
transmitter.
SPRUH22I – April 2012 – Revised November 2019
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Initialization and Configuration
M3 Inter-Integrated Circuit (I2C) Interface
1497