C28 External Interrupt 3 Counter Register (Xint3Ctr); System Pll Configuration (Syspllctl) Register; C28 External Interrupt 3 Counter Register (Xint3Ctr) Field Descriptions; System Pll Configuration (Syspllctl) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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1.13.5.19 C28 External Interrupt 3 Counter Register (XINT3CTR)

Figure 1-82. C28 External Interrupt 3 Counter Register (XINT3CTR)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-93. C28 External Interrupt 3 Counter Register (XINT3CTR) Field Descriptions
Bit Field
15-0 INTCTR

1.13.5.20 System PLL Configuration (SYSPLLCTL) Register

31
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-94. System PLL Configuration (SYSPLLCTL) Register Field Descriptions
Bit Field
31-2 Reserved
1 SPLLCLKEN
0 SPLLEN
SPRUH22I – April 2012 – Revised November 2019
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Value Description
C28 XINT3 Counter
This is a free running 16-bit up-counter that is clocked at the C28SYSCLKOUT rate. The counter
value is reset to 0x0000 when a valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be reset by the selected POLARITY
edge as selected in the respective interrupt control register. When the interrupt is disabled, the
counter will stop. The counter is a free-running counter and will wrap around to zero when the max
value is reached. The counter is a read only register and can only be reset to zero by a valid
interrupt edge or by the C28 SYSRSN reset.
Figure 1-83. System PLL Configuration (SYSPLLCTL) Register
Reserved
R-0:0
Value Description
Reserved
System PLL Clock Enable
System PLL bypassed or included in the PLLSYSCLK path.
This bit decides if the system PLL is bypassed when PLLSYSCLK is generated.
0 System PLL is bypassed; clock to the system is a direct feed from X1.
1 System PLL is on the clock path to PLLSYSCLK; PLLSYSCLK is the PLL multiplied clock.
System PLL Enable
This bit decides if the system PLL is enabled or not.
0 System PLL is powered off; clock to the system is a direct feed from X1.
1 System PLL is enabled and clock to the system will depend on SYSPLLMULT and SYSPLLCLKEN
register bit configuration.
Copyright © 2012–2019, Texas Instruments Incorporated
INTCTR
R-0:0
Reserved
R-0:0
Reserved
R-0:0 R-0
2
System Control Registers
8
1 0
SPLLCLKEN SPLLEN
R/W-0 R/W-0
System Control and Interrupts
0
16
217