Flash Bank Pump Control Register 2 (Fpac2); Flash Module Access Control Register (Fmac); Flash Bank Pump Control Register 2 (Fpac2) Field Descriptions; Flash Module Access Control Register (Fmac) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 5-91. Flash Bank Pump Control Register 1 (FPAC1) Field Descriptions (continued)

Flash Bank Pump Control Register 2 (FPAC2)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-92. Flash Bank Pump Control Register 2 (FPAC2) Field Descriptions

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-93. Flash Module Access Control Register (FMAC) Field Descriptions

SPRUH22I – April 2012 – Revised November 2019

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Flash Charge Pump Fallback Power Mode. This bit selects what power mode the charge pump

enters after the pump active grace period (PAGP) counter has timed out.

Sleep (all pump circuits disabled)

Active (all pump circuits active)

Note: As the pump is shared between both M3 and C28x banks, if an access is made either to the

M3 bank or C28x bank, the value of this bit changes to 1 (active).

Figure 5-88. Flash Bank Pump Control Register 2 (FPAC2)

Pump Active Grace Period. This register contains the starting count value for the PAGP mode down

counter. Any access to flash memory causes the counter to reload with the PAGP value. After the

last access to flash memory, the down counter delays from 0 to 65535 prescaled M3 SYSCLK clock

cycles before entering one of the charge pump fallback power modes as determined by PUMPPWR

in the FPAC1 register.

Note: The PAGP down counter is clocked by the same prescaled clock as the BAGP down counter

which is divided by 16 of input M3 SYSCLK.

Figure 5-89. Flash Module Access Control Register (FMAC)

BANKID. Controls the bank on which the Flash FSM operations will be performed. For these

devices, the value of this field will be 0 as there is only one bank in Master subsystem.

Flash Registers

Internal Memory

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