Edge-Count Mode Example - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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2.3.2.3 Input Edge-Count Mode
NOTE: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In edge-count mode, the timer is configured as a 24-bit down-counter including the optional prescaler with
the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the lower bits in
the GPTMTnILR register. In this mode, the timer is capable of capturing three types of events: rising edge,
falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register
must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the
GPTMCTL register. During initialization, the GPTMTnMATCHR and GPTMTnPMR registers are configured
so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the
GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for
event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts the CnMRIS
bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
In addition to generating interrupts, a µDMA trigger can be generated. The µDMA trigger is enabled by
configuring and enabling the appropriate µDMA channel. See Channel Configuration in the Micro Direct
Memory Access (µDMA) chapter.
After the match value is reached, the counter is then reloaded using the value in GPTMTnILR and
GPTMTnPR registers, and stopped because the GPTM automatically clears the TnEN bit in the
GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is
re-enabled by software.
Figure 2-3 shows how Input edge-count mode works. In this case, the timer start value is set to
GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events
are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit after the
current count matches the value in the GPTMTnMATCHR register.
Count
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
SPRUH22I – April 2012 – Revised November 2019
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Figure 2-3. Edge-Count Mode Example
Timer stops,
flags
asserted
Copyright © 2012–2019, Texas Instruments Incorporated
Functional Description
Timer reload
on nextcycle
Ignored Ignored
M3 General-Purpose Timers
303