Sample Rate Generator 1 Register (Srgr1); Sample Rate Generator 2 Register (Srgr2); Sample Rate Generator 1 Register (Srgr1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

McBSP Registers
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-82. Sample Rate Generator 1 Register (SRGR1) Field Descriptions
Bit Field
15-8 FWID
7-0 CLKGDV

15.12.7.2 Sample Rate Generator 2 Register (SRGR2)

The sample rate generator 2 register (SRGR2) is shown in
15 14
GSYNC Reserved
R/W-0 R/W-0
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1132
C28 Multichannel Buffered Serial Port (McBSP)
Figure 15-73. Sample Rate Generator 1 Register (SRGR1)
CLKGDV
Value Description
0-FFh Frame-synchronization pulse width bits for FSG
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization
signal, FSG. For frame-synchronization pulses on FSG, (FWID + 1) is the pulse width in CLKG
cycles. The eight bits of FWID allow a pulse width of 1 to 256 CLKG cycles:
0 ≤ FWID ≤ 255
1 ≤ (FWID + 1) ≤ 256 CLKG cycles
The period between the frame-synchronization pulses on FSG is defined by the FPER bits.
0-FFh Divide-down value for CLKG. The sample rate generator can accept an input clock signal and
divide it down according to CLKGDV to produce an output clock signal, CLKG. The frequency
of CLKG is:
CLKG frequency = (Input clock frequency)/ (CLKGDV + 1)
The input clock is selected by the SCLKME and CLKSM bits:
SCLKME CLKSM
0 0
0 1
1 0
1 1
Figure 15-74. Sample Rate Generator 2 Register (SRGR2)
13 12
CLKSM FSGM
R/W-1 R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
FWID
R/W-0
R/W-1
Input Clock For
Sample Rate Generator
Reserved
LSPCLK
Signal on MCLKR pin
Signal on MCLKX pin
Figure 15-74
11
FPER
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
and described in Table 15-83.
FPER
R/W-0
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8
0
8
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