Mpu Region Number (Mpunumber) Register; Mpu Region Base Address (Mpubase) Register; Mpu Region Number (Mpunumber) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 25-55. MPU Control (MPUCTRL) Register Field Descriptions (continued)
Bit Field
0 ENABLE
25.7.3 MPU Region Number (MPUNUMBER) Register, offset 0xD98
The MPU Region Number (MPUNUMBER) register selects which memory region is referenced by the
MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers.
Normally, the required region number should be written to this register before accessing the MPUBASE or
the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register
with the VALID bit set. This write updates the value of the REGION field.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-56. MPU Region Number (MPUNUMBER) Register Field Descriptions
Bit Field
31-3 Reserved
2-0 NUMBER
25.7.4 MPU Region Base Address (MPUBASE) Register, Offset 0xD9c-0xDB4
The MPU Region Base Address (MPUBASE) register defines the base address of the MPU region
selected by the MPU Region Number (MPUNUMBER) register and can update the value of the
MPUNUMBER register. To change the current region number and update the MPUNUMBER register,
write the MPUBASE register with the VALID bit set.
The ADDR field is bits 31: Nof the MPUBASE register. Bits ( N-1):5 are reserved. The region size, as
specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of
Nwhere:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this
case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a
multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value Description
MPU Enable. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is
unpredictable.
0 0 The MPU is disabled.
1 1 The MPU is enabled.
Figure 25-49. MPU Region Number (MPUNUMBER) Register
Reserved
R-0
Value Description
Reserved
MPU Region to Access
0 This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The
MPU supports eight memory regions.
Figure 25-50. MPU Region Base Address (MPUBASE) Register
ADDR
R/W-0
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Memory Protection Unit (MPU) Register Descriptions
5 4
VALID
W-0
Cortex-M3 Peripherals
3 2 0
NUMBER
R/W-0
3 2 0
reserved REGION
R-0 R/W-0
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