Table of Contents
Advertisement
www.ti.com
19.6.15 Ethernet MAC Transmission Request (MACTR) Register, offset 0x038
The Ethernet MAC Transmission Request (MACTR) register enables software to initiate the transmission
of the frame currently located in the TX FIFO. Once the frame has been transmitted from the TX FIFO or a
transmission error has been encountered, the NEWTX bit is automatically cleared.
Figure 19-19. Ethernet MAC Transmission Request (MACTR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-18. Ethernet MAC Transmission Request (MACTR) Register Field Descriptions
Bit
Field
31-1
Reserved
0
NEWTX
19.6.16 Ethernet MAC Timer Support (MACTS) Register, offset 0x03C
The Ethernet MAC Timer Support (MACTS) register enables software to enable highly precise timing on
the transmission and reception of frames. To enable this function, set the TSEN bit.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-19. Ethernet MAC Timer Support (MACTS) Register Field Descriptions
Bit
Field
31-1
Reserved
0
TSEN
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Reserved
R-0
Value
Description
Reserved
New Transmission
0
The transmission has completed.
1
Initiates an Ethernet transmission once the packet has been placed in the TX FIFO
If early transmission is being used (see the MACTHR register), this bit does not need to be set.
Figure 19-20. Ethernet MAC Timer Support (MACTS) Register
Reserved
R-0
Value
Description
Reserved
Time Stamp Enable
0
No effect.
1
The TX and RX interrupts are routed to the CCP inputs of General-Purpose Timer 3.
Copyright © 2012–2019, Texas Instruments Incorporated
Ethernet MAC Register Descriptions
M3 Ethernet Media Access Controller (EMAC)
1
0
NEWTX
R/W-0
1
0
TSEN
R/W-0
1401
Advertisement
Chapters
Table of Contents
