Mtoc Ipc Commands - Texas Instruments Concerto F28M35 Series Technical Reference Manual

C-Boot ROM Description
6.6.9.3 MTOC IPC Command – IPC Commands Supported by C-Boot ROM
Table 6-21 shows all the IPC commands supported by C-Boot ROM. The description column shows what
C-Boot ROM does to service the IPC command.
The 'Value' column shows the value that has to be written to MTOCIPCCOM register to send the
command in the MTOCIPCCOM column. The MTOCIPCADDR and MTOCIPCDATAW columns show how
these registers should be initialized by the master or how C-Boot ROM interprets these register contents
to be – for the respective command in the MTOCIPCCOM column.
The MTOCIPCDATAR and MTOCIPCFLG[31] columns show the values set by C-Boot ROM based on the
command sent by the master.
The heading ROW also shows the READ-WRITE permissions for each register for each core. If any of the
commands results in a failure, then the MTOCIPCDATAR register contents tell why the command failed.
This is explained in
Value (M3 - R/W, C28X R)
MTOCIPCCOM
0 MASTER_IPC_MTOC_COM
MAND_ILLEGAL
1 MASTER_IPC_MTOC_SET_
BITS_16
2 MASTER_IPC_MTOC_SET_
BITS_32
3 MASTER_IPC_MTOC_CLEA
R_BITS_16
4 MASTER_IPC_MTOC_CLEA
R_BITS_32
5 MASTER_IPC_MTOC_DATA
_WRITE_16
6 MASTER_IPC_MTOC_DATA
_WRITE_32
7 MASTER_IPC_MTOC_DATA
_READ_16
8 MASTER_IPC_MTOC_DATA
_READ_32
9 MASTER_IPC_MTOC_SET_
BITS_PROTECTED_16
10 MASTER_IPC_MTOC_SET_
BITS_PROTECTED_32
11 MASTER_IPC_MTOC_CLEA
R_BITS_PROTECTED_16
12 MASTER_IPC_MTOC_CLEA
R_BITS_PROTECTED_32
13 MASTER_IPC_MTOC_DATA
_WRITE_PROTECTED_16
588
ROM Code and Peripheral Booting
Section 6.6.9.4.
Table 6-21. MTOC IPC Commands
MTOCIPCADDR MTOCIPCDATAW
(M3 - R/W, (M3 - R/W, C28X
B.C28X R) R)
DON'T CARE DON'T CARE
Address of the 16 Data in
bit location MTOCIPCDATAW[
15:0]
Address of the 32 Data;
bit register
Address of the 16 Data in
bit register MTOCIPCDATAW[
15:0]
Address of the 32 Data
bit register
Address of the 16 Data in
bit register MTOCIPCDATAW[
15:0]
Address of the 32 Data
bit register
Address of the 16 DON'T CARE
bit register
Address of the 32 DON'T CARE
bit register
Address of the 16 Data in
bit register MTOCIPCDATAW[
15:0]
Address of the 32 Data;
bit register
Address of the 16 Data in
bit register MTOCIPCDATAW[
15:0]
Address of the 32 Data
bit register
Address of the 16 Data in
bit register MTOCIPCDATAW[
15:0]
Copyright © 2012–2019, Texas Instruments Incorporated
MTOCIPCDATAR MTOCIPCFLG[31]
(M3 - R, C28X = ?
R/W) (MTOCIPCFLAG[
0] = 0)
Section 6.6.9.4 0x01 = Command
failure
Data read back 0x00 = Command
from address after success
write
Data read back 0x00 = Command
from address after success
write
Data read back 0x00 = Command
after write success
Data read back 0x00 = Command
after write success
Data read back 0x00 = Command
from the address success
after write
Data read back 0x00 = Command
from the address success
after write
Data in 0x00 = Command
MTOCIPCDATAR[ success
15:0]
32 bit data 0x00 = Command
success
Data read back 0x00 = Command
from address after success
write
Data read back 0x00 = Command
from address after success
write
Data read back 0x00 = Command
after write success
Data read back 0x00 = Command
after write success
Data read back 0x00 = Command
from the address success
SPRUH22I – April 2012 – Revised November 2019
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Description
Illegal command
*(address) |= data;
*(address) |= data;
*(address) &= ~data;
*(address) &= ~data;
*(address) = data;
*(address) = data;
MTOCIPCDATAR[15:0]
= *(address);
Only 16 bit read from
address
MTOCIPCDATAR[31:0]
= *(address);
32 bits read from
address
EALLOW;
*(address) |= data;
EDIS;
EALLOW;
*(address) |= data;
EDIS;
EALLOW;
*(address) &= ~data;
EDIS;
EALLOW;
*(address) &= ~data;
EDIS;
EALLOW;
*(address) = data;
EDIS;