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1.4.1 Entering WIR Mode
In the boot procedure, M-Boot ROM (after releasing the control subsystem and ACIB out of reset), reads
EMU0 (bit 0) and EMU1 (bit 1) bits of the MWIR register. If the values match the WIR_MODE_YES value
as per
Table 1-7
then M-Boot ROM enters a wait forever loop as shown in
C-Boot ROM is executed after the control subsystem is out of reset. C-Boot ROM reads EMU0 and EMU1
bits of the CWIR register. If the values match the WIR_MODE_YES values as per the
Boot ROM enters a wait forever loop as shown in
There is more than one way to put the master subsystem and/or control subsystem in WIR mode. The
user has to make sure that EMU0 and EMU1 bits in the MWIR register and/or the CWIR register are set to
the WIR_MODE_YES value and run the boot ROM. To achieve this, the user can:
•
Set EMU0 and EMU1 pins on the device to the WIR_MODE_YES value and give an XRS reset to the
device. This will latch the state of EMU0 and EMU1 pins in the WIR registers and execute the boot
ROM(s) in each subsystem. Please see the device-specific data manual for more details on the pin
locations.
•
Directly write the WIR_MODE_YES value to the EMU0 and EMU1 bits in the MWIR and CWIR
registers. This will put both the master and control subsystems in WIR mode when boot ROM(s) are
run after reset. Both EMU0 and EMU1 are R/W type bits and are reset to the actual state of EMU0 and
EMU1 pins on XRS reset or whenever the sample bit is set in the respective WIR registers to re-
sample these pins. So, it is not necessary to set the sample bit and force a software reset or debugger
reset.
•
Set EMU0 and EMU1 pins to the WIR_MODE_YES values and set the sample bit in each WIR mode
register and give a software reset or debugger reset to the device.
Figure 1-2
shows how each boot ROM puts respective CPU in WIR mode.
SPRUH22I – April 2012 – Revised November 2019
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Table 1-7. EMU0/1 Pin Values for WIR Mode
EMU0
0
0
1
1
Copyright © 2012–2019, Texas Instruments Incorporated
EMU1
0
1
WIR_MODE_YES
0
1
Figure
1-2.
WIR Mode
WIR mode
NO
NO
NO
Figure
1-2.
Table
1-7, then C-
System Control and Interrupts
93
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