Dma Channel Request Mask Set (Dmareqmaskset), Offset 0X020; Dma Channel Request Mask Clear (Dmareqmaskclr), Offset 0X024; Dma Channel Enable Set (Dmaenaset), Offset 0X028; Dma Channel Request Mask Set (Dmareqmaskset) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 16-24. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Register Field Descriptions
Bit Field
31-0 CLR[n]

16.7.9 DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020

Each bit of the DMAREQMASKSET register represents the corresponding µDMA channel. Setting a bit
disables µDMA requests for the channel. Reading the register returns the request mask status. When a
µDMA channel's request is masked, that means the peripheral can no longer request µDMA transfers. The
channel can then be used for software-initiated transfers.
Figure 16-18. DMA Channel Request Mask Set (DMAREQMASKSET) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-25. DMA Channel Request Mask Set (DMAREQMASKSET) Register Field Descriptions
Bit Field
31-0 SET[n]

16.7.10 DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024

Each bit of the DMAREQMASKCLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAREQMASKSET register.
Figure 16-19. DMA Channel Request Mask Clear (DMAREQMASKCLR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-26. DMA Channel Request Mask Clear (DMAREQMASKCLR) Register Field Descriptions
Bit Field
31-0 CLR[n]

16.7.11 DMA Channel Enable Set (DMAENASET), offset 0x028

Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit enables
the corresponding µDMA channel. Reading the register returns the enable status of the channels. If a
channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for
software-initiated transfers.
SPRUH22I – April 2012 – Revised November 2019
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Value Description
Channel [n] Useburst Clear
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that
μDMA channel [n] responds to single and burst requests.
Value Description
Channel [n] Request Mask Set
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAREQMASKCLR register.
0 The peripheral associated with channel [n] is enabled to request μDMA transfers.
1 The peripheral associated with channel [n] is not able to request μDMA transfers. Channel [n] may
be used for software-initiated transfers.
Value Description
Channel [n] Request Mask Clear
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that
the peripheral associated with channel [n] is enabled to request μDMA transfers.
Copyright © 2012–2019, Texas Instruments Incorporated
SET[n]
R/W-0
CLR[n]
W
M3 Micro Direct Memory Access ( µDMA)
µDMA Register Descriptions
0
0
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