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Functional Description
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C
Slave Raw Interrupt Status (I2CSRIS) register.
22.3.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by setting
the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL
signals from the master and slave modules are tied together.
22.3.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and slave
mode.
22.3.5.1 I2C Master Command Sequences
Figure 22-7
through
1490
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-12
show the command sequences available for the I2C master.
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
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