Cx Dedram Configuration Register 1 (Cxdrcr1); Cx Dedram Configuration Register 1 (Cxdrcr1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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5.2.1 M3 RAM Configuration Registers
5.2.1.1

Cx DEDRAM Configuration Register 1 (CxDRCR1)

31
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-9. Cx DEDRAM Configuration Register 1 (CxDRCR1) Field Descriptions
Bit Field
31-11 Reserved
10 CPUWRPROTC1
9 Reserved
8 FETCHPROTC1
7-3 Reserved
2 CPUWRPROTC0
1 Reserved
0 FETCHPROTC0
SPRUH22I – April 2012 – Revised November 2019
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Figure 5-4. Cx DEDRAM Configuration Register 1 (CxDRCR1)
Reserved
R-0
Reserved
R-0
Value Description
Reserved
CPU Write Protection C1
0 M3 CPU write allowed to C1 RAM block.
1 M3 CPU write not allowed to C1 RAM block.
Reserved
CPU Fetch Protection C1
0 M3 CPU Fetch allowed from C1 RAM block.
1 M3 CPU Fetch not allowed from C1 RAM block.
Reserved
CPU Write Protection C0
0 M3 CPU write allowed to C0 RAM block.
1 M3 CPU write not allowed to C0 RAM block.
Reserved
CPU Fetch Protection C0
0 M3 CPU Fetch allowed from C0 RAM block.
1 M3 CPU Fetch not allowed from C0 RAM block.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11 10
CPUWRPROT
C1
R/W-0
3 2
CPUWRPROT
C0
R/W-0
RAM Control Module Registers
16
9 8
Reserved FETCHPROTC
1
R-0 R/W-0
1 0
Reserved FETCHPROTC
0
R-0 R/W-0
Internal Memory
437