Set The Srg Input Clock Polarity; Transmitter Configuration; Programming The Mcbsp Registers For The Desired Transmitter Operation; Register Bits Used To Set The Srg Input Clock Polarity - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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15.8.22 Set the SRG Input Clock Polarity

Table 15-46. Register Bits Used to Set the SRG Input Clock Polarity
Register Bit
PCR 1
PCR 0
15.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
The sample rate generator can produce a clock signal (CLKG) and a frame-synchronization signal (FSG)
for use by the receiver, the transmitter, or both. To produce CLKG and FSG, the sample rate generator
must be driven by an input clock signal derived from the CPU clock or from an external clock on the CLKX
or MCLKR pin. If you use a pin, choose a polarity for that pin by using the appropriate polarity bit (CLKXP
for the MCLKX pin, CLKRP for the MCLKR pin). The polarity determines whether the rising or falling edge
of the input clock generates transitions on CLKG and FSG.

15.9 Transmitter Configuration

To configure the McBSP transmitter, perform the following procedure:
1. Place the McBSP/transmitter in reset (see
2. Program the McBSP registers for the desired transmitter operation (see
3. Take the transmitter out of reset (see

15.9.1 Programming the McBSP Registers for the Desired Transmitter Operation

The following is a list of important tasks to be performed when you are configuring the McBSP transmitter.
Each task corresponds to one or more McBSP register bit fields.
• Global behavior:
– Set the transmitter pins to operate as McBSP pins.
– Enable/disable the digital loopback mode.
– Enable/disable the clock stop mode.
– Enable/disable transmit multichannel selection.
• Data behavior:
– Choose 1 or 2 phases for the transmit frame.
– Set the transmit word length(s).
– Set the transmit frame length.
– Enable/disable the transmit frame-synchronization ignore function.
– Set the transmit companding mode.
– Set the transmit data delay.
SPRUH22I – April 2012 – Revised November 2019
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Name Function
CLKXP MCLKX pin polarity
CLKXP determines the input clock polarity when the MCLKX pin
supplies the input clock (SCLKME = 1 and CLKSM = 1).
CLKXP = 0
CLKXP = 1
CLKRP MCLKR pin polarity
CLKRP determines the input clock polarity when the MCLKR pin
supplies the input clock (SCLKME = 1 and CLKSM = 0).
CLKRP = 0
CLKRP = 1
Section
Copyright © 2012–2019, Texas Instruments Incorporated
Rising edge on MCLKX pin generates transitions
on CLKG and FSG.
Falling edge on MCLKX pin generates transitions
on CLKG and FSG.
Falling edge on MCLKR pin generates transitions
on CLKG and FSG.
Rising edge on MCLKR pin generates transitions
on CLKG and FSG.
Section 15.9.2).
15.9.2).
C28 Multichannel Buffered Serial Port (McBSP)
Receiver Configuration
Reset
Type Value
R/W
R/W
Section 15.9.1).
0
0
1097