Run Mode Clock Gating Control Register 3 (Rcgc3); Sleep Mode Clock Gating Control Register 3 (Scgc3); Run Mode Clock Gating Control Register 3 (Rcgc3) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com
Table 1-124. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Field Descriptions (continued)
Bit Field
2 GPIOC
1 GPIOB
0 GPIOA

1.13.7.22 Run Mode Clock Gating Control Register 3 (RCGC3)

Figure 1-114. Run Mode Clock Gating Control Register 3 (RCGC3)
31
Reserved
R-0:0
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-125. Run Mode Clock Gating Control Register 3 (RCGC3) Field Descriptions
Bit Field
31-26 Reserved
25 CAN1
24 CAN0
23-1 Reserved
0 UART4

1.13.7.23 Sleep Mode Clock Gating Control Register 3 (SCGC3)

Figure 1-115. Sleep Mode Clock Gating Control Register 3 (SCGC3)
31
Reserved
R-0:0
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Value Description
GPIOC Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOC module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOB Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOB module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOA Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOA module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
26 25
CAN1
R/W-0 R/W-0
Reserved
R-0:0
Value Description
Reserved
CAN1 Clock Gating Control in Run Mode
This bit controls the clock gating for the CAN1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
CAN0 Clock Gating Control in Run Mode
This bit controls the clock gating for the CAN0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
UART4 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART4 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
26 25
CAN1
R/W-0 R/W-0
Reserved
R-0:0
Copyright © 2012–2019, Texas Instruments Incorporated
24 23
CAN0
24 23
CAN0
System Control Registers
Reserved
R-0:0
1 0
UART4
R/W-0
Reserved
R-0:0
1
UART4
R/W-0
System Control and Interrupts
16
16
0
239