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Inter Processor Communications (IPC)
Once the C28x is done with configuring the clock settings and performing any operations at that
configured clock frequency, it should release mastership of the clock configuration registers by writing a
value of "00" in the CCLKREQUEST semaphore so that the M3 can gain control when needed. In case of
a conflict when both the M3 and C28x simultaneously try to gain control over the clock configuration
registers by writing appropriate values to the above semaphore registers, the M3 will gain the mastership.
1.12.9 Free Running Counter
A 64-bit free running counter is present in the device and can be used to timestamp IPC events between
processors. This 64-bit MIPCCOUNTERL(32-bit)/ MIPCCOUNTERH(32-bit) is clocked by the shared
resources clock and is readable by the M3 and the C28x on their respective memory maps. These counter
registers are reset to zero on reset.
Because the counter is 64-bits and the M3/C28x can only read 32-bits at a time, an issue can arise when
reading the counters separately. If the low 32-bit counter is read just before it overflows and then the high
32-bit counter is read, the combined values read will be incorrect. To solve this, a snapshot for the high
32-bits counter is taken when a read is performed on the MIPCCOUNTERL register. When the M3/C28x
reads the MIPCOUNTERH, the snapshot is fed back to the user instead of the current value in the
MIPCOUNTERH register. Therefore, the user application software must always read MIPCCOUNTERL
first and then read MIPCCOUNTERH.
The MIPCCOUNTERL/H is stopped only when both the M3 and C28 CPUs are halted (not the low power
halt-mode). If either core is executing, the counter runs. It is suggested that the user application should
disable interrupts when reading the counters.
164
System Control and Interrupts
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SPRUH22I – April 2012 – Revised November 2019
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